An analog-to-digital converter (ADC) is a device that takes an analog data signal and converts it into a digital code, i.e. digitizes or quantizes the analog signal. An ADC is a key building block in mixed-mode integrated circuits (ICs). Once the analog signal is converted into the digital domain, complicated signal processing functions can be performed with easier handling and improved noise immunity. In some instances, power dissipation can be reduced since many ADCs are implemented in a deep submicron CMOS process.
ADCs may employ a wide variety of architectures, such as the integrating, successive-approximation, flash, and the delta-sigma architectures. Recently, the pipelined analog-to-digital converter (ADC) has become a popular ADC architecture for use in high-speed applications such as CCD imaging, ultrasound medical imaging, digital video, and communication technologies such as cable modems and fast Ethernet. Pipelined ADCs are typically chosen because of their high accuracy, high throughput rate, and low power consumption. Moreover, the pipelined architecture generally provides better performance for a given power and semiconductor die area than other ADC architectures.
An example of a conventional k-stage pipelined ADC (100) is shown in FIG. 1. As shown in the figure, the conventional k-stage pipelined ADC (100) includes an array of k gain stages (102) and a decoder logic circuit (104). Each of the gain stages (102) is connected in series to the previous gain stage (102). Each gain stage (102) is also connected to the decoder logic circuit (104).
In operation, an analog input voltage (Vin) is provided to the first gain stage (102). The first gain stage (102) samples the analog input voltage (Vin) and converts it to a first digital coefficient (n1). The first coefficient (n1) is processed by the decoder logic circuit (104) to provide the Most Significant Bit (MSB) of a digital data representation of the analog input voltage (Vin). The first gain stage (102) also converts the first digital coefficient (n1) back to an analog representation. The analog representation is subtracted from the sampled analog input voltage (Vin) and multiplied by a gain multiplier to provide a residue voltage. The residue voltage (Vres(1)) from the first gain stage (102) becomes the analog input voltage to the next gain stage (102) of the pipeline. That is, Vin (2)=Vres(1). The residue voltage (Vres(i)) continues through the pipeline of gain stages (102), providing another digital coefficient (ni) based on the digital representation of the input to that gain stage, as described above.
The overall digital representation of the analog voltage input (Vin) is obtained by concatenating the k digital coefficients (n1 through nk) from the array of k gain stages (102) through the decoder logic circuit (104). Digital error correction logic is typically used to improve the accuracy of conversion by providing overlap between the quantization ranges of adjacent gain stages (102) in the pipeline. An architecture that makes use of this correction to a 1-bit per stage pipelined ADC is a 1.5-bit per stage pipelined topology.
FIG. 2 is a graph illustrating ideal transfer characteristics of a 1.5-bit per stage conventional pipelined ADC such as illustrated in FIG. 1. In the 1.5-bit architecture, there are two thresholds or transition points in the transfer curve, resulting in three operating regions. Each stage of the 1.5-bit architecture effectively converts only one bit of information. The extra region (as compared to a 1-bit per stage topology) is used for redundancy. That is, the extra bit of information is combined with the digital outputs from subsequent gain stages (102) in the pipeline to generate another bit. The comparator offset from each stage does not introduce any error on the transfer curve at the final digital output by doing digital error correction as described above, when the offset is within its correction range.
As shown in FIG. 2, the input voltage (Vin) appears along the x-axis and illustrates that the resolvable input range of the ADC is given by: −Vref<Vin<+Vref. Two transition points appear along the x-axis. The first transition point occurs at Vin equal to −Vref/4 and the second transition point occurs at Vin equal to +Vref/4. The two transition points divide the operating range for the input voltage (Vin) into three operating regions, where two bits (00, 01, and 10) of the digital output of each stage characterize the entire range. Further, the slope of each curve reflects the gain multiplier employed in the gain stage (102) of FIG. 1.
Operationally, the gain stage (102) examines the input (Vin(i)) and determines whether the input is less than the first transition point, −Vref/4. If Vin(i) is less than the first transition point (−Vref/4) then the digital code output for the gain stage (102) is 00. Similarly, a digital output code of 01 is generated for Vin(i) between the first transition point, −Vref/4, and the second transition point (+Vref/4). If Vin(i) is greater than the second transition point, +Vref/4, the ideal transfer characteristic generates a digital output code of 10.
Moreover, the output residue voltage (Vres(i)) is generated by the following transfer function:Vres(i)=2M·Vin(i)−Di·Vref  (EQ 1)
where M is the number of effective bits that are being generated by stage i, 2M represents the gain multiplier for the gain stage (102), and Di is a constant determined by the digital representation of the analog input voltage (Vin), having possible values of −1, 0, and 1. For the 1.5-bit per stage ADC, the number of effective bits (M) is one. The output residue voltage (Vres(i)) generated at the ith gain stage (102) becomes the analog input voltage (Vin (i+1)) to the next gain stage (102).